Physical Design Engineer

at  in  Bangalore, India | Posted on 24 August, 2015
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Job Description
Job Description:
Creates bottoms-up elements of chip design including but not limited to: Device, cell, and block-level layouts, Block-level floor plans, abstract view generation, RC extraction, and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, clock generation, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, RV, DFM, Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing, execution, and verification of complex chips development and execution of project methodologies and/or flow developments 
  • You should possess a technical certification or a technical degree in Electronics, Electrical engineering with experience in Layout Designing.


  • Proficiency in multiple levels of layout design which includes data path, register files, and standard cell designs
  • Proficiency in floor planning activities which include FUB-unit level assembly, routing, and integration of custom blocks in to the FC floorplan
  • Ability to comprehend issues of RC delay, electro-migration, self-heating, and cross capacitance
  • Ability to recognize failure prone layout structures, and proactively contact engineers for guidance and produce electrically robust layout

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About Company

Intel Corporation is an American multinational corporation headquartered in Santa Clara, California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue.

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