Physical Design Engineer in Analalog IP group

at  in  Bangalore, India | Posted on 27 August, 2015
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Job Description
Job Role  :
  • Working closely with the Design and Micro-Arch team in studying, understanding, analyzing the micro-arch specifications and own Partition/Block level, IP level layout.
  • Interacting with micro-architects and the design team in areas of Logic synthesis, Layout methodology development, and Performance/Layout verification to ensure that layout goals are met.
  • Participating in Partition and IP floorplanning and implementing the physical layout for the IP.
  • Verifying and ensuring that Area/Power/Performance specifications are met.
  • Ownership of synthesis in order to estimate power and timing constraints at IP, partition and full chip level
  • Work directly with back-end team members and support floor planning, APR and timing closures


Qualification :
  • You should possess a Bachelor's and/or a Master's degree in Electrical Engineering and/or Computer Engineering with knowledge and at least more than six years of experience in VLSI physical design.
  • Knowledge of microelectronics designs, semiconductor device physics, CMOS process and physical layout
  • Good hands-on Knowledge on EDA tools like Synopsys design tools in the field of logic and physical design
  • Good knowledge in scripting languages specially in Perl* and Tcl*
  • Familiarity with hardware description language such as Verilog* or System Verilog*


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Intel Corporation is an American multinational corporation headquartered in Santa Clara, California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue.

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